4x4 Bit Multiplier Designs using Different CMOS Schematics, and their Comparison

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Kaynat Rana
Asim Niaz
Sumbol Hanif
Muhammad Touqeer Ali


In this paper, low power and high speed 4x4 bit multipliers are presented. The full adder and a half adder blocks used in these multipliers are designed using adiabatic and transmission gate techniques respectively. The multiplier circuit is implemented using Dadda algorithm. This circuit is simulated in 1P-9M Low-K UMC 90nm CMMOS process technology (cadence Virtuoso). The circuit operates at a clock frequency of 5.46 and 8.54 GHz and dynamic average power of 2.667 and 1.139 mW respectively, at room temperature of 27˚C and 1.9V supply voltage.

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